1. Field of the Invention
The invention relates to the field of integrated circuit packaging and failure analysis and more particularly to a method and device for removing a heatspreader from an integrated circuit package such as a flip chip.
2. Description of the Relevant Art
Integrated circuits are universally familiar devices found in an enormous variety of consumer, business, and industrial machines and products. An integrated circuit is an electronic device typically fabricated on a single crystal substrate preferably comprised of silicon or other suitable semiconductor material. Semiconductors such as silicon possess characteristics useful in the manufacturing of integrated circuits including a resistivity that can be easily manipulated over an extremely wide range of values and a compatibility with oxidation processes that facilitate formation of high quality electrically insulating films. During the fabrication process, thousands or millions of circuit elements such as transistors, diodes, resistors, and capacitors are simultaneously formed on the substrate through a series of well known fabrication steps during which the conductances of precisely defined regions within the substrate are altered to achieve a particular circuit element and to isolate the individual circuit elements from one another. The individual circuit elements are then selectively interconnected to each other using one or more photolithographically defined interconnect layers to produce a circuit having the desired functionality. Typically, multiple integrated circuits are fabricated simultaneously on a single, round slice or wafer of the semiconductor material with a typical diameter of 150, 200, or 300 mm (although other wafer diameters are sometimes encountered). After the completion of the fabrication process, the wafer is tested to determine which of the integrated circuits are functional. The wafer is then "diced" or sawed into the individual integrated circuits and the functional integrated circuits are placed in a protective casing or package.
Although modern integrated circuits incorporate literally millions of transistors, the signals flowing to and from the integrated circuit (the I/O signals) are necessarily limited in number because each l/O signal requires a conductive and relatively large I/O pad to which an external connection, such as a connection to a printed circuit board on which the integrated circuit is mounted, can be made. Thus, the packaging of an integrated circuit involves not only a means for protecting the integrated circuit from physical damage, but also a method of making external connections to the I/O pads of the device. For much of the history of the semiconductor industry, the predominant method of connecting the I/O pads of the packaged integrated circuit to the external environment utilized wire bond technology. In a typical wire bond arrangement, a first end of a thin and electrically conductive wire is attached to an I/O pad while the second end is attached to a lead frame or other packaging structure that provides a conductive path to the integrated circuit leads as well as physical support for the integrated circuit. The device and lead frame are then encased in the packaging material (e.g. plastic or ceramic) such that the leads are externally accessible and suitable for mounting on a circuit board or other structure.
As fabrication process technology has evolved to the point that minimum transistor geometries are now routinely less than 0.5 .mu.m, devices of ever greater complexity (i.e. more transistors) are being produced on a decreasing area of silicon (or other suitable substrate material). Market demands for smaller, faster, and more complex devices that integrate multiple sub-systems on a single chip have resulted in devices with an ever increasing lead or pin count. The simultaneous demands for higher pin counts and smaller packages has placed greater emphasis on packaging technology. Flip chip technology has evolved as a popular packaging technique to achieve large pin counts in small packages. Flip chips do away with wire bonding by packaging the device with its active surface "flipped" with respect to the orientation of predecessor packaging technologies and connecting the l/O pads of the device directly to the printed circuit board.
Referring to FIG. 1, a typical flip chip 120 is shown. Flip chip 120 includes am integrated circuit 102 contained in an integrated circuit package (ICP) 122. Typically, ICP 122 provides a cavity into which integrated circuit 102 is placed. Integrated circuit 102 is fabricated on a substrate 105, preferably comprised of single crystal silicon, that includes an active surface 104 and a backside 106. Active surface 104 refers to the surface proximal to which the active elements of the integrated circuit are fabricated. A thermal paste (represented in FIG. 1 by reference numeral 126) is typically applied to integrated circuit 102 to improve the heat dissipation characteristics of flip chip 120. Suitable thermal pastes are commercially available from a variety of sources and are well known in the field of semiconductor packaging. In many flip chip processes, the ICP cavity is sealed with a heatspreader 124 attached to the top of ICP 122. As their name implies, heatspreaders are designed to further dissipate heat generated by integrated circuit 102 to prevent the device from overheating and suffering permanent damage. The high operating speeds of modern integrated circuits and the tremendous number of transistors now available on a single chip have resulted in devices that produce an unprecedented amount of thermal energy during operation. Without the assistance of thermally efficient packages and accompanying heat sinks, these high speed devices would tend to overheat and self destruct. Heatspreaders facilitate heat dissipation by providing a material of high thermal conductivity in close proximity to the device.
Despite the best efforts of semiconductor manufacturers to eliminate randomly generated particles and other defects that can render devices non-functional, some fraction of the integrated circuits produced by a manufacturer will fail to operate properly. In addition, a number of devices that are initially functional will fail at some point after the device has been packaged and possibly after the device has been installed in an application. An important function within any semiconductor fabrication facility involves investigating and identifying the sources of yield limiting phenomena, early lifetime failures, and other problems and reducing or eliminating those sources. The process of achieving these goals is commonly referred to as failure analysis. One of the unintended consequences of the relatively recent explosion in the wide spread use of miniaturized packages is the increased burden placed on failure analysis personnel to properly study devices that fail after they have been packaged. One can imagine that, at some point in the failure analysis process, it is necessary to visually inspect (with or without the aid of a microscope and various other analysis tools) the integrated circuit itself. Once a device has been packaged, however, visual inspection of that device presents significant problems, not the least of which is the process of trying to remove or open the package to allow access to the device without physically damaging the device itself. These considerations take on additional significance when one considers the relatively low level of failures associated with integrated circuits. Because the number of samples of devices failing in the field or after packaging is typically well below 0.1%, it becomes extremely important to gather as much information as possible from each sample of an actual failure. Accordingly, it is important to be able to gain physical and visual access to integrated circuits that fail after they have been packaged to perform proper failure analysis.